Revised CARMA Correlator FPGA Configurations
Kevin P. Rauch (University of Maryland, College Park)

This memo provides technical information on a variety of FPGA-level design
details for the revised CARMA correlator digital hardware. This includes
descriptions of the board-level FPGA layout, communication paths, and baseline
partitioning; specifics of fundamental VHDL design components, and their
distribution by FPGA; and the FPGA memory map and control register 
specification.